add more plumbing for SPI on BeagleBone

[Adafruit_Blinka-hackapet.git] / src / adafruit_blinka / microcontroller / beaglebone_black / pin.py

diff --git a/src/adafruit_blinka/microcontroller/beaglebone_black/pin.py b/src/adafruit_blinka/microcontroller/beaglebone_black/pin.py
index 8e9a46b5304e660d3b4c9a23da6931e2a0a2d585..a379f1dfc438d58c2377dcaeded26b3422b77dc2 100644 (file)
--- a/src/adafruit_blinka/microcontroller/beaglebone_black/pin.py
+++ b/src/adafruit_blinka/microcontroller/beaglebone_black/pin.py
@@ -132,8 +132,31 @@ USR3 = Pin('USR3')
 SCL = Pin('P9_19')
 SDA = Pin('P9_20')
 
+# Refer to header default pin modes
+# http://beagleboard.org/static/images/cape-headers.png
+#
+# P9_17 (SPI0_CSO => CE0) enables peripheral device
+# P9_18 (SPI0_D1 => MOSI) outputs data to peripheral device
+# P9_21 (SPIO_DO => MISO) receives data from peripheral device
+# P9_22 (SPI0_SCLK => SCLK) outputs clock signal
+# 
+# Use config-pin to set pin mode for SPI pins
+# https://github.com/beagleboard/bb.org-overlays/tree/master/tools/beaglebone-universal-io
+# config-pin p9.17 spi_cs
+# config-pin p9.18 spi
+# config-pin p9.21 spi
+# config-pin p9.22 spi_sclk
+#
+CE0 = Pin('P9_17')
+MOSI = Pin('P9_18')
+MISO = Pin('P9_21')
+SCLK = Pin('P9_22')
+#CircuitPython naming convention for SPI Clock
+SCK = Pin('P9_22')
+
 # ordered as spiId, sckId, mosiId, misoId
-spiPorts = ()
+#spiPorts = ((0, SCLK, MOSI, MISO), (1, SCLK_1, MOSI_1, MISO_1))
+spiPorts = ((0, SCLK, MOSI, MISO), (1, SCLK, MOSI, MISO))
 
 # ordered as uartId, txId, rxId
 uartPorts = (
@@ -141,6 +164,6 @@ uartPorts = (
 )
 
 i2cPorts = (
-    (1, SCL, SDA),
+    (2, SCL, SDA),
 )