Merge pull request #276 from makermelissa/master

[Adafruit_Blinka-hackapet.git] / src / adafruit_blinka / microcontroller / ft232h / spi.py

diff --git a/src/adafruit_blinka/microcontroller/ft232h/spi.py b/src/adafruit_blinka/microcontroller/ft232h/spi.py
index a260e7206e42ed2f4e89f8468e481d01f37f7301..bd4a53be1b435e20ab7e0cb9ba72379ee789a5a0 100644 (file)
--- a/src/adafruit_blinka/microcontroller/ft232h/spi.py
+++ b/src/adafruit_blinka/microcontroller/ft232h/spi.py
@@ -1,12 +1,20 @@
+"""SPI Class for FT232H"""

 from adafruit_blinka.microcontroller.ft232h.pin import Pin
 
 from adafruit_blinka.microcontroller.ft232h.pin import Pin
 

+# pylint: disable=protected-access

 class SPI:
 class SPI:

+    """Custom SPI Class for FT232H"""
+

     MSB = 0
 
     def __init__(self):
     MSB = 0
 
     def __init__(self):

+        # pylint: disable=import-outside-toplevel

         from pyftdi.spi import SpiController
         from pyftdi.spi import SpiController

+
+        # pylint: enable=import-outside-toplevel
+

         self._spi = SpiController(cs_count=1)
         self._spi = SpiController(cs_count=1)

-        self._spi.configure('ftdi:///1')
+        self._spi.configure("ftdi://ftdi:ft232h/1")

         self._port = self._spi.get_port(0)
         self._port.set_frequency(100000)
         self._port._cpol = 0
         self._port = self._spi.get_port(0)
         self._port.set_frequency(100000)
         self._port._cpol = 0


@@ -14,8 +22,19 @@ class SPI:
         # Change GPIO controller to SPI
         Pin.ft232h_gpio = self._spi.get_gpio()
 
         # Change GPIO controller to SPI
         Pin.ft232h_gpio = self._spi.get_gpio()
 

-    def init(self, baudrate=100000, polarity=0, phase=0, bits=8,
-                  firstbit=MSB, sck=None, mosi=None, miso=None):
+    # pylint: disable=too-many-arguments
+    def init(
+        self,
+        baudrate=100000,
+        polarity=0,
+        phase=0,
+        bits=8,
+        firstbit=MSB,
+        sck=None,
+        mosi=None,
+        miso=None,
+    ):
+        """Initialize the Port"""

         self._port.set_frequency(baudrate)
         # FTDI device can only support mode 0 and mode 2
         # due to the limitation of MPSSE engine.
         self._port.set_frequency(baudrate)
         # FTDI device can only support mode 0 and mode 2
         # due to the limitation of MPSSE engine.


@@ -25,11 +44,15 @@ class SPI:
             raise ValueError("Only SPI phase 0 is supported by FT232H.")
         self._port._cpha = phase
 
             raise ValueError("Only SPI phase 0 is supported by FT232H.")
         self._port._cpha = phase
 

+    # pylint: enable=too-many-arguments
+

     @property
     def frequency(self):
     @property
     def frequency(self):

+        """Return the current frequency"""

         return self._port.frequency
 
     def write(self, buf, start=0, end=None):
         return self._port.frequency
 
     def write(self, buf, start=0, end=None):

+        """Write data from the buffer to SPI"""

         end = end if end else len(buf)
         chunks, rest = divmod(end - start, self._spi.PAYLOAD_MAX_LENGTH)
         for i in range(chunks):
         end = end if end else len(buf)
         chunks, rest = divmod(end - start, self._spi.PAYLOAD_MAX_LENGTH)
         for i in range(chunks):


@@ -37,18 +60,31 @@ class SPI:
             chunk_end = chunk_start + self._spi.PAYLOAD_MAX_LENGTH
             self._port.write(buf[chunk_start:chunk_end])
         if rest:
             chunk_end = chunk_start + self._spi.PAYLOAD_MAX_LENGTH
             self._port.write(buf[chunk_start:chunk_end])
         if rest:

-            self._port.write(buf[-1*rest:])
+            self._port.write(buf[-1 * rest :])

 
 

+    # pylint: disable=unused-argument

     def readinto(self, buf, start=0, end=None, write_value=0):
     def readinto(self, buf, start=0, end=None, write_value=0):

+        """Read data from SPI and into the buffer"""

         end = end if end else len(buf)
         end = end if end else len(buf)

-        result = self._port.read(end-start)
+        result = self._port.read(end - start)

         for i, b in enumerate(result):
         for i, b in enumerate(result):

-            buf[start+i] = b
+            buf[start + i] = b
+
+    # pylint: enable=unused-argument

 
 

-    def write_readinto(self, buffer_out, buffer_in,  out_start=0, out_end=None, in_start=0, in_end=None):
+    # pylint: disable=too-many-arguments
+    def write_readinto(
+        self, buffer_out, buffer_in, out_start=0, out_end=None, in_start=0, in_end=None
+    ):
+        """Perform a half-duplex write from buffer_out and then
+        read data into buffer_in
+        """

         out_end = out_end if out_end else len(buffer_out)
         in_end = in_end if in_end else len(buffer_in)
         out_end = out_end if out_end else len(buffer_out)
         in_end = in_end if in_end else len(buffer_in)

-        result = self._port.exchange(buffer_out[out_start:out_end],
-                                     in_end-in_start, duplex=True)
+        result = self._port.exchange(
+            buffer_out[out_start:out_end], in_end - in_start, duplex=True
+        )

         for i, b in enumerate(result):
         for i, b in enumerate(result):

-            buffer_in[in_start+i] = b
+            buffer_in[in_start + i] = b
+
+    # pylint: enable=too-many-arguments